Instruction Sets

MPEG2 video decompression on a multiprocessing VLIW microprocessor

Computer Architecture / Data Compression / Video Compression / CPU / Instruction Set Architecture / VLIW / Decoding / Instruction Sets / VLIW / Decoding / Instruction Sets

MPEG2 video decompression on a multiprocessing VLIW microprocessor

Computer Architecture / Data Compression / Video Compression / CPU / Instruction Set Architecture / VLIW / Decoding / Instruction Sets / VLIW / Decoding / Instruction Sets

Exploiting temporal locality in network traffic using commodity multi-cores

Automata / Intrusion Detection Systems / Intrusion Detection / Case Study / Pattern Matching / Redundancy / Acceleration / Intrusion Detection System / UAV payloads / Computer Network Security / String Matching / Finite state machines / Network Traffic / Instruction Sets / Finite State Machine / Redundancy / Acceleration / Intrusion Detection System / UAV payloads / Computer Network Security / String Matching / Finite state machines / Network Traffic / Instruction Sets / Finite State Machine

Polarization Energy on a Cluster of Multicores

Parallel Algorithms / Approximation Algorithms / Resource Allocation / Drug Design / Polarisation / Proteins / Multicore Processing / Instruction Sets / Proteins / Multicore Processing / Instruction Sets

Energy-efficient hybrid wakeup logic

Computer Science / Computer Architecture / Energy Consumption / Energy efficiency / Broadcasting / Hybrid / Energy Saving / Indexing / Low Power / Low Power Electronics / Energy efficient / Logic Design / Energy Efficiency / Indexation / Micro-Architecture / Registers / Instruction Sets / Hybrid / Energy Saving / Indexing / Low Power / Low Power Electronics / Energy efficient / Logic Design / Energy Efficiency / Indexation / Micro-Architecture / Registers / Instruction Sets

MPEG-2 video decompression on a multiprocessing VLIW microprocessor

Computer Architecture / Data Compression / Video Compression / CPU / Instruction Set Architecture / VLIW / Decoding / Instruction Sets / VLIW / Decoding / Instruction Sets

A video compression case study on a reconfigurable VLIW architecture

Video Compression / Motion estimation / Hardware / Case Study / Kernel / VLIW / Bandwidth / Coarse Grained Soil / Instruction Sets / VLIW / Bandwidth / Coarse Grained Soil / Instruction Sets

Parallel VLSI detailed routing using general-purpose computing on graphics processing unit

Routing / VLSI / CPU / Very Large Scale Integration / Gpgpu / Instruction Sets / Central Processing Unit / Integrated Circuit Design / Instruction Sets / Central Processing Unit / Integrated Circuit Design

Energy-efficient issue queue design

Distributed Computing / Computer Hardware / Instruction Scheduling / Low Power / Low Power Electronics / Energy efficient / Instruction Sets / Electrical And Electronic Engineering / Power Dissipation / Energy efficient / Instruction Sets / Electrical And Electronic Engineering / Power Dissipation

TCEMC: A co-design flow for application-specific multicores

Parallel Programming / Parallel Processing / Programming / Embedded / System on Chip / Multicore Processing / Instruction Sets / Integrated Circuit Design / Multicore Processing / Instruction Sets / Integrated Circuit Design

A Step towards Energy Efficient Computing: Redesigning a Hydrodynamic Application on CPU-GPU

High Performance Computing / Energy / Finite element method / FEM / Linear Algebra / Finite Element Analysis / Power / Sparse Matrices / BLAST / Hydrodynamics / Kernel / Force / Registers / Bandwidth / Instruction Sets / Finite Element Analysis / Power / Sparse Matrices / BLAST / Hydrodynamics / Kernel / Force / Registers / Bandwidth / Instruction Sets

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